How to make assertions in Chisel be just warnings and not stop simulation
We have added assertions to our Chisel code, but we only want them to warn, not stop the simulation. Is there a way to tell Chisel to do this?
For example:
assert(x(1) =/= nxt_val(1))
We want this to just give us a warning, so we can collect the log, to find places where clock gating is most effective.
riscv chisel
asked Nov 12 '18 at 18:24
seanhalleseanhalle
389117
add a comment |
We have added assertions to our Chisel code, but we only want them to warn, not stop the simulation. Is there a way to tell Chisel to do this?
For example:
assert(x(1) =/= nxt_val(1))
We want this to just give us a warning, so we can collect the log, to find places where clock gating is most effective.
riscv chisel
asked Nov 12 '18 at 18:24
seanhalleseanhalle
389117
add a comment |
We have added assertions to our Chisel code, but we only want them to warn, not stop the simulation. Is there a way to tell Chisel to do this?
For example:
assert(x(1) =/= nxt_val(1))
We want this to just give us a warning, so we can collect the log, to find places where clock gating is most effective.
riscv chisel
asked Nov 12 '18 at 18:24
seanhalleseanhalle
389117
We have added assertions to our Chisel code, but we only want them to warn, not stop the simulation. Is there a way to tell Chisel to do this?
For example:
assert(x(1) =/= nxt_val(1))
We want this to just give us a warning, so we can collect the log, to find places where clock gating is most effective.
riscv chisel
riscv chisel
asked Nov 12 '18 at 18:24
seanhalleseanhalle
389117
asked Nov 12 '18 at 18:24
seanhalleseanhalle
389117
asked Nov 12 '18 at 18:24
seanhalleseanhalle
389117
asked Nov 12 '18 at 18:24
seanhalleseanhalle
389117
asked Nov 12 '18 at 18:24
seanhalleseanhalle
389117
389117
add a comment |
add a comment |
2 Answers
2
active
oldest
votes
Can you just write a method that you pass the condition and perhaps a behavior flag.
object warnAssert {
def apply(condition: Bool, message: String = "", isFatal: Boolean = false)
(isFatal, message.isEmpty)
case (true, true) => assert(condition)
case (true, false) => assert(condition, message)
case (false, _) => when(bool) printf("Warning: %sn", message) // line number should get included here
answered Nov 13 '18 at 17:39
Chick MarkleyChick Markley
1,515810
add a comment |
Chick's answer is reasonable, although I suspect you're looking for something that Verilog simulators register as an error rather than a printf.
Unfortunately the simulation construct support in FIRRTL is pretty primitive--assert emitting $fatal is an example of this. We generally have dealt with this via FIRRTL transforms, or simulator-specific stuff (implementing see our Verilator testing top for example). As discussed at the CCC, I think we should invest more effort in better simulation libraries. If you have ideas and suggestions, it would be super helpful if you could package them up in an RFC: https://github.com/freechipsproject/chisel3/issues.
answered Nov 16 '18 at 19:37
jkoenigjkoenig
2,608717
add a comment |
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2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
Can you just write a method that you pass the condition and perhaps a behavior flag.
object warnAssert {
def apply(condition: Bool, message: String = "", isFatal: Boolean = false)
(isFatal, message.isEmpty)
case (true, true) => assert(condition)
case (true, false) => assert(condition, message)
case (false, _) => when(bool) printf("Warning: %sn", message) // line number should get included here
answered Nov 13 '18 at 17:39
Chick MarkleyChick Markley
1,515810
add a comment |
Can you just write a method that you pass the condition and perhaps a behavior flag.
object warnAssert {
def apply(condition: Bool, message: String = "", isFatal: Boolean = false)
(isFatal, message.isEmpty)
case (true, true) => assert(condition)
case (true, false) => assert(condition, message)
case (false, _) => when(bool) printf("Warning: %sn", message) // line number should get included here
answered Nov 13 '18 at 17:39
Chick MarkleyChick Markley
1,515810
add a comment |
Can you just write a method that you pass the condition and perhaps a behavior flag.
object warnAssert {
def apply(condition: Bool, message: String = "", isFatal: Boolean = false)
(isFatal, message.isEmpty)
case (true, true) => assert(condition)
case (true, false) => assert(condition, message)
case (false, _) => when(bool) printf("Warning: %sn", message) // line number should get included here
answered Nov 13 '18 at 17:39
Chick MarkleyChick Markley
1,515810
Can you just write a method that you pass the condition and perhaps a behavior flag.
object warnAssert {
def apply(condition: Bool, message: String = "", isFatal: Boolean = false)
(isFatal, message.isEmpty)
case (true, true) => assert(condition)
case (true, false) => assert(condition, message)
case (false, _) => when(bool) printf("Warning: %sn", message) // line number should get included here
answered Nov 13 '18 at 17:39
Chick MarkleyChick Markley
1,515810
answered Nov 13 '18 at 17:39
Chick MarkleyChick Markley
1,515810
answered Nov 13 '18 at 17:39
Chick MarkleyChick Markley
1,515810
answered Nov 13 '18 at 17:39
Chick MarkleyChick Markley
1,515810
1,515810
add a comment |
add a comment |
Chick's answer is reasonable, although I suspect you're looking for something that Verilog simulators register as an error rather than a printf.
Unfortunately the simulation construct support in FIRRTL is pretty primitive--assert emitting $fatal is an example of this. We generally have dealt with this via FIRRTL transforms, or simulator-specific stuff (implementing see our Verilator testing top for example). As discussed at the CCC, I think we should invest more effort in better simulation libraries. If you have ideas and suggestions, it would be super helpful if you could package them up in an RFC: https://github.com/freechipsproject/chisel3/issues.
answered Nov 16 '18 at 19:37
jkoenigjkoenig
2,608717
add a comment |
Chick's answer is reasonable, although I suspect you're looking for something that Verilog simulators register as an error rather than a printf.
Unfortunately the simulation construct support in FIRRTL is pretty primitive--assert emitting $fatal is an example of this. We generally have dealt with this via FIRRTL transforms, or simulator-specific stuff (implementing see our Verilator testing top for example). As discussed at the CCC, I think we should invest more effort in better simulation libraries. If you have ideas and suggestions, it would be super helpful if you could package them up in an RFC: https://github.com/freechipsproject/chisel3/issues.
answered Nov 16 '18 at 19:37
jkoenigjkoenig
2,608717
add a comment |
Chick's answer is reasonable, although I suspect you're looking for something that Verilog simulators register as an error rather than a printf.
Unfortunately the simulation construct support in FIRRTL is pretty primitive--assert emitting $fatal is an example of this. We generally have dealt with this via FIRRTL transforms, or simulator-specific stuff (implementing see our Verilator testing top for example). As discussed at the CCC, I think we should invest more effort in better simulation libraries. If you have ideas and suggestions, it would be super helpful if you could package them up in an RFC: https://github.com/freechipsproject/chisel3/issues.
answered Nov 16 '18 at 19:37
jkoenigjkoenig
2,608717
Chick's answer is reasonable, although I suspect you're looking for something that Verilog simulators register as an error rather than a printf.
Unfortunately the simulation construct support in FIRRTL is pretty primitive--assert emitting $fatal is an example of this. We generally have dealt with this via FIRRTL transforms, or simulator-specific stuff (implementing see our Verilator testing top for example). As discussed at the CCC, I think we should invest more effort in better simulation libraries. If you have ideas and suggestions, it would be super helpful if you could package them up in an RFC: https://github.com/freechipsproject/chisel3/issues.
answered Nov 16 '18 at 19:37
jkoenigjkoenig
2,608717
answered Nov 16 '18 at 19:37
jkoenigjkoenig
2,608717
answered Nov 16 '18 at 19:37
jkoenigjkoenig
2,608717
answered Nov 16 '18 at 19:37
jkoenigjkoenig
2,608717
2,608717
add a comment |
add a comment |
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