LLVM Instruction Scheduling in RISC-V
I am looking at instruction scheduling in LLVM for RISC-V backend. I understood there are two ways of scheduling (ScheduleDAGRRList & MachineScheduler). From debug logs i can RISC-V uses ScheduleDAGRRList approach.
Is MachineScheduler is better than ScheduleDAGRRList? If so, how can i enable MachineScheduler for RISC-V ?
I tried llc -enable-misched file.ll
, but with no luck.
clang llvm scheduler riscv llc
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I am looking at instruction scheduling in LLVM for RISC-V backend. I understood there are two ways of scheduling (ScheduleDAGRRList & MachineScheduler). From debug logs i can RISC-V uses ScheduleDAGRRList approach.
Is MachineScheduler is better than ScheduleDAGRRList? If so, how can i enable MachineScheduler for RISC-V ?
I tried llc -enable-misched file.ll
, but with no luck.
clang llvm scheduler riscv llc
add a comment |
I am looking at instruction scheduling in LLVM for RISC-V backend. I understood there are two ways of scheduling (ScheduleDAGRRList & MachineScheduler). From debug logs i can RISC-V uses ScheduleDAGRRList approach.
Is MachineScheduler is better than ScheduleDAGRRList? If so, how can i enable MachineScheduler for RISC-V ?
I tried llc -enable-misched file.ll
, but with no luck.
clang llvm scheduler riscv llc
I am looking at instruction scheduling in LLVM for RISC-V backend. I understood there are two ways of scheduling (ScheduleDAGRRList & MachineScheduler). From debug logs i can RISC-V uses ScheduleDAGRRList approach.
Is MachineScheduler is better than ScheduleDAGRRList? If so, how can i enable MachineScheduler for RISC-V ?
I tried llc -enable-misched file.ll
, but with no luck.
clang llvm scheduler riscv llc
clang llvm scheduler riscv llc
asked Nov 15 '18 at 7:22
harryharry
16
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