Generate 1000 MHz clock in VHDL from 100 MHz
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Is it possible to generate a 1000 MHz clock from a 100 MHz in VHDL ?
I want to create a 1ns counter and my fpga has a 100 MHz clock!
vhdl fpga xilinx
asked Nov 12 at 7:35
Reza Mohammadi
43
add a comment |
up vote
0
down vote
favorite
Is it possible to generate a 1000 MHz clock from a 100 MHz in VHDL ?
I want to create a 1ns counter and my fpga has a 100 MHz clock!
vhdl fpga xilinx
asked Nov 12 at 7:35
Reza Mohammadi
43
1
Hi! First of all, have you checked if your component can achieve such high frequency, register to register ?
– grorel
Nov 12 at 8:37
Normally, Xilinx FPGAs are limited around 700-800 MHz. Higher frequencies can not be handled by clock buffers, except for I/O clock buffers.
– Paebbels
Nov 12 at 22:18
add a comment |
up vote
0
down vote
favorite
up vote
0
down vote
favorite
Is it possible to generate a 1000 MHz clock from a 100 MHz in VHDL ?
I want to create a 1ns counter and my fpga has a 100 MHz clock!
vhdl fpga xilinx
asked Nov 12 at 7:35
Reza Mohammadi
43
Is it possible to generate a 1000 MHz clock from a 100 MHz in VHDL ?
I want to create a 1ns counter and my fpga has a 100 MHz clock!
vhdl fpga xilinx
vhdl fpga xilinx
asked Nov 12 at 7:35
Reza Mohammadi
43
asked Nov 12 at 7:35
Reza Mohammadi
43
asked Nov 12 at 7:35
Reza Mohammadi
43
asked Nov 12 at 7:35
Reza Mohammadi
43
asked Nov 12 at 7:35
Reza Mohammadi
43
43
1
Hi! First of all, have you checked if your component can achieve such high frequency, register to register ?
– grorel
Nov 12 at 8:37
Normally, Xilinx FPGAs are limited around 700-800 MHz. Higher frequencies can not be handled by clock buffers, except for I/O clock buffers.
– Paebbels
Nov 12 at 22:18
add a comment |
1
Hi! First of all, have you checked if your component can achieve such high frequency, register to register ?
– grorel
Nov 12 at 8:37
Normally, Xilinx FPGAs are limited around 700-800 MHz. Higher frequencies can not be handled by clock buffers, except for I/O clock buffers.
– Paebbels
Nov 12 at 22:18
1
1
Hi! First of all, have you checked if your component can achieve such high frequency, register to register ?
– grorel
Nov 12 at 8:37
Hi! First of all, have you checked if your component can achieve such high frequency, register to register ?
– grorel
Nov 12 at 8:37
Normally, Xilinx FPGAs are limited around 700-800 MHz. Higher frequencies can not be handled by clock buffers, except for I/O clock buffers.
– Paebbels
Nov 12 at 22:18
Normally, Xilinx FPGAs are limited around 700-800 MHz. Higher frequencies can not be handled by clock buffers, except for I/O clock buffers.
– Paebbels
Nov 12 at 22:18
add a comment |
1 Answer
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Clock generation is usually done with Phase Locked Loop (PLL) or Digital Clock Manager (DCM), available in the FPGA as dedicated FPGA hardware resources.
If you want to scale up a clock, like going from 100 MHz to 1000 MHz, then you definitely need to use the dedicated FPGA hardware resources in order to get a stable and manageable implementation.
However, a clock of 1000 MHz is very likely too fast for use in any general logic, like a standard counter. Clocks that fast are typically only used for some very special purposes like internally in a SERDES etc.
So you probably have to consider some different way to implement the required functionality.
answered Nov 12 at 8:51
Morten Zilmer
12.3k21637
add a comment |
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1 Answer
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1 Answer
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active
oldest
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active
oldest
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active
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up vote
3
down vote
Clock generation is usually done with Phase Locked Loop (PLL) or Digital Clock Manager (DCM), available in the FPGA as dedicated FPGA hardware resources.
If you want to scale up a clock, like going from 100 MHz to 1000 MHz, then you definitely need to use the dedicated FPGA hardware resources in order to get a stable and manageable implementation.
However, a clock of 1000 MHz is very likely too fast for use in any general logic, like a standard counter. Clocks that fast are typically only used for some very special purposes like internally in a SERDES etc.
So you probably have to consider some different way to implement the required functionality.
answered Nov 12 at 8:51
Morten Zilmer
12.3k21637
add a comment |
up vote
3
down vote
Clock generation is usually done with Phase Locked Loop (PLL) or Digital Clock Manager (DCM), available in the FPGA as dedicated FPGA hardware resources.
If you want to scale up a clock, like going from 100 MHz to 1000 MHz, then you definitely need to use the dedicated FPGA hardware resources in order to get a stable and manageable implementation.
However, a clock of 1000 MHz is very likely too fast for use in any general logic, like a standard counter. Clocks that fast are typically only used for some very special purposes like internally in a SERDES etc.
So you probably have to consider some different way to implement the required functionality.
answered Nov 12 at 8:51
Morten Zilmer
12.3k21637
add a comment |
up vote
3
down vote
up vote
3
down vote
Clock generation is usually done with Phase Locked Loop (PLL) or Digital Clock Manager (DCM), available in the FPGA as dedicated FPGA hardware resources.
If you want to scale up a clock, like going from 100 MHz to 1000 MHz, then you definitely need to use the dedicated FPGA hardware resources in order to get a stable and manageable implementation.
However, a clock of 1000 MHz is very likely too fast for use in any general logic, like a standard counter. Clocks that fast are typically only used for some very special purposes like internally in a SERDES etc.
So you probably have to consider some different way to implement the required functionality.
answered Nov 12 at 8:51
Morten Zilmer
12.3k21637
Clock generation is usually done with Phase Locked Loop (PLL) or Digital Clock Manager (DCM), available in the FPGA as dedicated FPGA hardware resources.
If you want to scale up a clock, like going from 100 MHz to 1000 MHz, then you definitely need to use the dedicated FPGA hardware resources in order to get a stable and manageable implementation.
However, a clock of 1000 MHz is very likely too fast for use in any general logic, like a standard counter. Clocks that fast are typically only used for some very special purposes like internally in a SERDES etc.
So you probably have to consider some different way to implement the required functionality.
answered Nov 12 at 8:51
Morten Zilmer
12.3k21637
answered Nov 12 at 8:51
Morten Zilmer
12.3k21637
answered Nov 12 at 8:51
Morten Zilmer
12.3k21637
answered Nov 12 at 8:51
Morten Zilmer
12.3k21637
12.3k21637
add a comment |
add a comment |
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1
Hi! First of all, have you checked if your component can achieve such high frequency, register to register ?
– grorel
Nov 12 at 8:37
Normally, Xilinx FPGAs are limited around 700-800 MHz. Higher frequencies can not be handled by clock buffers, except for I/O clock buffers.
– Paebbels
Nov 12 at 22:18